The TranSwitch PHAST®-3P (TXC-06203) is an STM-1/STS-3c section, line and path overhead termination device that performs ATM and PPP PHY-layer processing. It provides either a SDH/SONET pseudo-ECL bit-serial interface or a byte-wide parallel interface on the line side. The serial interface provides 155 MHz clock recovery and clock synthesis, and the section and line overhead bytes in the data are processed. The PHAST-3P performs pointer tracking and POH byte processing. TOH (RSOH and MSOH) and POH bytes are provided in RAM for microprocessor access or via TOH and POH interfaces. The POH bytes can be inserted from RAM, the serial POH interface, or a mate PHAST-3P device for line and path ring applications. The terminal interface is UTOPIA level 2 for ATM cells or level 2P for packets. UTOPIA bus width can be 8-bit or 16-bit, Single-PHY and Multi-PHY operation are supported.
For testing, the PHAST-3P provides boundary scan, B2 and B3 BER measurements, programmable BIP error mask generation, and line loopback. The device provides either Motorola or Intel microprocessor access. Performance counters can be configured to be saturating or roll-over. The interrupts, with mask bits, can be programmed for positive, negative, or positive/negative alarm transitions or positive levels. A software polling register is also provided.
PHAST is a Registered Trademark of TranSwitch Corporation
Features
ATM cells over SDH/SONET
ATM cell delineation
Single-bit error detection and multiple-bit error detection
ATM Scrambler/descrambler option (x43+1)
Idle cell discard
Cell filtering (GFC, PTI and CLP fields)
Four-cell receive and transmit FIFOs (programmable-depth transmit FIFO)
Rate adaptation using idle cells
HEC generator with optional COSET addition
PPP (IP packets) over SDH/SONET
Octet stuffing/destuffing
PPP Scrambler/descrambler option (x43+1)
Data inversion option
Invalid frame detection
Short frame and programmable long frame detection
CRC-16 or CRC-32 detection/generation
CRC pass-through option
256-byte receive and transmit FIFOs
Bit-serial P-ECL SDH/SONET line interface
Bit-parallel SDH/SONET line interface
Section, line and path overhead byte processing
Receive pointer tracking
AIS, LOP, NDF and false pointer detection
RAM access to section, line and path overhead bytes
Section, line and path overhead byte insertion sources:
RAM, interfaces, ring (mate device) or receive side (e.g., RDI)
Supports 1+1 or 1:N APS applications
Interfaces:
TOH bytes with programmable byte marker pulse
K1/K2 APS bytes
E1 and E2 order wire bytes
Section data communications (D1-D3) bytes
Line data communications (D4-D12) bytes
POH bytes (VC-4 or each STS-1)
Alarm Indication Port (AIP) for line/path ring operation
Scan and drive leads (two each)
Terminal side 8-bit or 16-bit UTOPIA level 2 interface (with additional signals for PPP)
Single-PHY or Multi-PHY
Motorola-compatible or Intel-compatible microprocessor interface
Boundary scan and line loopback
Single +3.3 volt, ±5% power supply; 5 volt input signals tolerance
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ASPEN/PHAST-3P Users Manual
BSDL File for Rev. D and Earlier Devices
Device Driver
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