Summary

THIS PRODUCT IS MANUFACTURING DISCONTINUED AND IS NO LONGER AVAILABLE FROM TRANSWITCH CORPORATION. ADVANCED TRANSWITCH PRODUCTS WITH ENHANCED FEATURES ARE OFTEN AVAILABLE. FILES ARE PROVIDED FOR SUPPORT PURPOSES ONLY.

The QT1F-Plus (TXC-03103C) is a four-channel DS1 (T1, 1.544 Mbit/s) framer designed with extended features for voice and data communications applications. AMI, B8ZS, and NRZ line codes are supported with full alarm detection and generation per ANSI T1M1.3. The transmit and receive sections of each of the four framers are independent, with individual slip buffers to allow operation in a wide range of switching and transmission products. D4 SF and ESF modes are provided per ANSI T1.403-1998 and AT&T PUB 62411, with per DS0 signaling and DS0 data access and control via a Motorola/Intel-compatible microprocessor interface. For ESF applications, each framer supplies a full duplex HDLC/bit-oriented message controller, supporting
back-to-back FDL messages in addition to onboard latching of all required performance parameters; minimal software overhead is required to support either ANSI T1.403-1998 or AT&T PUB 54016 protocols. Diagnostic, test, and maintenance functions are provided, including four loopback modes and boundary scan (IEEE 1149.1).

Applications

• SONET/SDH terminal or add/drop multiplexers supporting DS1 byte synchronous operation
  
• DCS, digital central office or remote digital terminals
  
• T1 multiplexers
  
• T1 and fractional T1 CSUs
  
• ATM products with integrated DS1 interfaces
  
• LAN routers with integrated DS1 interfaces
  
• Multichannel DS1 test equipment
  
• Internet Access Equipment with T1 and Fractional T1 Interfaces
  

Features

• 128-pin low profile plastic quad flat package
• Single +3.3 volt or +5.0 volt power supply
• Boundary scan capability (IEEE 1149.1)
• Processor forcing/monitoring of DS0s for maintenance purposes
• Local, line remote, payload remote and DS0 channel loopbacks, per DS0 channel inversion
• One-second interrupt input latches counter values and line events into shadow registers
• Motorola/Intel compatible microprocessor interface
• Detects, counts and forces line code errors (BPVs and excess zeros), CRC errors (ESF only), and frame bit errors
• Detects and forces Yellow and AIS alarms; detects OOF, Severely Errored Frame, and Change of Frame Alignment, detects AIS-CI
• Supports channel associated and robbed-bit signaling (enabled or processor forced on a per DS0 basis)
• Two-frame slip buffers in both receive and transmit directions
• Monitor function for frame pulse, clock and data
• Fractional T1 gapped clock
• Encodes/decodes AMI/B8ZS and forced ones density line codes
• D4 SF, ESF (including HDLC Link support), and transparent framing modes