Summary

PacketTrunk-4 is a TDMoIP/MPLS gateway device that transparently transports TDM trunks over IP/MPLS networks using the world's most popular standard for circuit emulation over IP/MPLS. The single-chip device includes robust clock recovery, encapsulation, jitter compensation, QoS support, and standards support for transport of structured and unstructured TDM signals over a packet-switched network (PSN). This packet processor serves as a building block for TDM over IP, TDM over MPLS, or TDM over switched Ethernet systems.

PacketTrunk-4's DPLL-based quad adaptive clock recovery block provides rapid frequency lock and highly accurate phase tracking. The block provides standards-compliant jitter and wander performance under real world PSN conditions by reconstructing the TDM clock based solely on inter-packet arrival time and jitter buffer fill level. During phase tracking, the chip optimizes jitter buffer levels to minimize latency.

The payload machine implements Constant Bit Rate (CBR) for circuit emulation, Variable Bit Rate (VBR) for loop emulation, and HDLC for efficient transfer or termination of frame-based traffic. Payload size is selectable over a wide range, giving end users maximum tradeoff flexibility between latency and overhead. PacketTrunk-4 is a highly-integrated ASIC designed for use in a wide variety of network access/edge applications that provides a scalable single-chip to multi-chip solution.

Applications

Carrier

• TDM services over Ethernet MAN, broadband wireless, CATV
  
• 2G / 2.5G cellular backhaul over IP/MPLS
  
• HDLC-based traffic (ex. Frame Relay) trunking over IP/MPLS
  
• T/E carrier grooming (via Ethernet backplane)
  
• PSTN-IP network bridging
  
• SS7 transport over IP
  

Enterprise

• Private line/toll bypass via Ethernet MAN
  
• TDM PBX migration to Ethernet MAN
  
• MTU/MDU
  

Features

• Four T1/E1/Serial or one T3/E3 TDM interfaces
• One 10/100 Ethernet IEEE 802.3 MAC, interface via MII/RMII/SMII/SSMII; HDX or FDX VLAN support per IEEE 802.1 p & Q
• Four independent advanced clock recovery blocks
• Recovered clock jitter and wander compliant to ITU-T G.823, G.824 (E1, T1 Jitter/Wander Control)
• 64 bundles with independent Tx/Rx queues, configurable jitter buffer depth, and optional redundancy via traffic duplication
• 128 DS0 cross connect
• Support for HDLC sub-rate channels of 2, 7, or 8 bits
• Lost/misordered packet compensation
• Glueless SDRAM interface up to 16 MB
• CBR, VBR, and HDLC payload types
• Compliant with latest IETF and MPLS Forum drafts
• RTOS-independent, abstracted host API source code
• 2.5v core, 3.3v I/O
• 256-pin PBGA, 27 x 27 mm (1.27 mm pitch)
• Test Access Port for IEEE 1149.1 boundary scan